`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:21:37 04/26/2013
// Design Name:   CPU
// Module Name:   C:/ASU/CSE320/Project3/tb_cpu.v
// Project Name:  Project3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: CPU
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_cpu;

	// Inputs
	reg [7:0] instr_data;
	reg instr_exec;
	reg clk;
	reg reset;
	reg [1:0] dis_addr;

	// Outputs
	wire [3:0] reg_data;

	// Instantiate the Unit Under Test (UUT)
	CPU uut (
		.instr_data(instr_data), 
		.instr_exec(instr_exec), 
		.clk(clk), 
		.reset(reset), 
		.reg_data(reg_data), 
		.dis_addr(dis_addr)
	);

	initial begin
		// Initialize Inputs
		instr_data = 0;
		instr_exec = 0;
		clk = 0;
		reset = 0;
		dis_addr = 0;

		// Wait 100 ns for global reset to finish
		#20;
      
		// Add stimulus here
		forever #5 clk <= ~clk;
	end
   initial begin
		@(posedge clk) reset = 0;
		@(posedge clk) reset = 0;
		@(posedge clk) reset = 1;
		//set. Test with input 0000_0111. Load 7 into A.
		@(posedge clk) instr_data = 8'h07; instr_exec = 1;
		@(posedge clk) instr_data = 8'h07; instr_exec = 0;
		#35
		//Test with input 0001_0011. Load 3 into B.
		@(posedge clk) instr_data = 8'b00010011; instr_exec = 1;
		@(posedge clk) instr_data = 8'b00010011; instr_exec = 0;
		#30
		//Test with input 0101_0001. B = A + B.
		@(posedge clk) instr_data = 8'b0101_0001; instr_exec = 1;
		@(posedge clk) instr_data = 8'b0101_0001; instr_exec = 0;
		#30
		//Test with input 0101_0001. B = A + B.
		@(posedge clk) reset = 1; instr_data = 8'b0101_0001; instr_exec = 1;
		@(posedge clk) reset = 1; instr_data = 8'b0101_0001; instr_exec = 0;
		#30
		//Test with input 0101_0001. B = A + B.
		@(posedge clk) reset = 1; instr_data = 8'b0101_0001; instr_exec = 1;
		@(posedge clk) reset = 1; instr_data = 8'b0101_0001; instr_exec = 0;
		#30
		//Test with input 1011_0001. D = A*B
		@(posedge clk) instr_data = 8'b1011_0001; instr_exec = 1;
		@(posedge clk) instr_data = 8'b1011_0001; instr_exec = 0;
		#30
		//Test with input 1111_1101. Compare D and B. load result into C.
		@(posedge clk) instr_data = 8'b1110_1100; instr_exec = 1;
		@(posedge clk) instr_data = 8'b1110_1100; instr_exec = 0;
		
		
		
	end
endmodule

